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preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 figure: mechanical dimensions 1 4096 mb ddr3 C sdram unbuffered ecc mini - u dimm 2 4 4 pin ecc mini - u dimm sg l 04g72 b 1b d 2sa - cc w r t - v 4 g b in fbga techn ology rohs compliant *) the refresh rate has to be doubled when 85c preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 2 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 this swissbit module is an industry standard 2 4 4 - pin ddr3 sdram ecc mini - dimm which is organized as x 72 high speed cmos memory arrays. the module uses internally configured oct al - bank ddr3 sdram devices. the module uses double data rate architecture to achieve high - speed operation. ddr3 sdram modules operate from a differential clock (ck and ck#). read and write accesses to a ddr3 sdram module is burst - oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. the burs t length is either four or eight locations. an auto precharge function can be enabled to provide a self - timed row precharge that is initiated at the end of a burst access. the ddr3 sdram devices have a multibank architecture which allows a concurrent opera tion that is providing a high effective bandwidth. a self refresh mode is provided and a power - saving power - down mode. all inputs and all full drive - strength outputs are sstl_15 compatible. the ddr3 sdram module uses the serial presence detect (spd) func tion implemented via serial eeprom using the standard i 2 c protocol. this nonvolatile storage device contains 256 bytes. the first 128 bytes are utilized by the so - u dimm manufacturer (swissbit) to identify the module type, the modules organization and seve ral timing parameters. the second 128 bytes are available to the end user. module configuration organization ddr3 sdrams used row addr. device bank select column addr. refresh module bank select 512 m x 72 bit 18 x 256 m x 8bit ( 2048m bit) 1 5 ba0, ba1, ba2 1 0 8k s0#, s1# module dimensions in mm 82.0 0 (long) x 30 .00 (high) x 5. 3 0 [max] (thickness with heat spreader ) timing parameters part number module density transfer rate memory clock/data bit rate latency sgl04g72b1bd2sa - cc w r t - v 4096 mb 10.6 gb/s 1.5 ns /1333mt/s 9 - 9 - 9 label info part number jedec module label sgl04g72b1bd2sa - ccwrt - v 4gb 2rx8 pc3 - 10600w - 9 - 11 - b0 figure 1: mechanical dime nsions
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 pin name a0 - 9, a11 C a14 address inputs a10/ap address input / autoprecharge bit ba0 C ba2 bank address inputs dq0 C dq63 data input / output cb0 C cb07 ecc check bits dm0 - dm8 input data mask dqs0 C dqs8 data strobe, positive line dqs0# - dqs8# data strobe, negative line (only used when differential data strobe mode is enabled) ras# row address strobe cas# column address strobe w e# write enable cke0 C cke1 clock enable s0#, s1# chip select ck0 C ck1 clock inputs, positive line ck0# - ck1# clock inputs, negative line event# temperature event: the event# pin is asserted by the temperature sensor when critical reset# reset sign al for ddr3 sdrams v dd supply voltage (1.5v 0.075v) v ref dq reference voltage: dq, dm (vdd/2) v ref ca reference voltage: control, command, and address (vdd/2) v ss ground v tt termination voltage: used for control, command, and address (vdd/2). v ddspd s erial eeprom positive power supply scl serial clock for presence detect sda serial data out for presence detect sa0 C sa1 presence detect address inputs odt0, odt1 on - die termination nc no connection
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 pin configuration frontside pin symbol pin sym bol pin symbol pin symbol 1 v tt 31 dq24 61 v dd 92 dq40 2 v refdq 32 dq25 62 a2 93 dq41 3 v ss 33 v ss 63 v dd 94 v ss 4 dq0 34 dqs3# 64 ck1 95 dqs5# 5 dq1 35 dqs3 65 ck1# 96 dqs5 6 v ss 36 v ss 66 v dd 97 v ss 7 dqs0# 37 dq26 67 v refca 98 dq42 8 dqs0 38 dq2 7 68 v dd 99 dq43 9 v ss 39 v ss 69 nc 100 v ss 10 dq2 40 cb0 70 v dd 101 dq48 11 dq3 41 cb1 71 a10 102 dq49 12 v ss 42 v ss 72 ba0 103 v ss 13 dq8 43 dqs8# 73 v dd 104 dqs6# 14 dq9 44 dqs8 74 we# 105 dqs6 15 v ss 45 v ss 75 cas# 106 v ss 16 dqs1# 46 cb2 76 v d d 107 dq50 17 dqs1 47 cb3 77 nc 108 dq51 18 v ss 48 v ss 78 nc 109 v ss 19 dq10 49 nc 79 v dd 110 dq56 20 dq11 50 r eset # 80 nc 111 dq57 21 v ss 51 cke0 81 nc 112 v ss 22 dq16 52 v dd 82 v ss 113 dqs7# 23 dq17 53 ba2 83 dq32 114 dqs7 24 v ss 54 nc 84 dq33 11 5 v ss 25 dqs2# 55 v dd 85 v ss 116 dq58 26 dqs2 56 a11 86 dqs4# 117 dq59 27 v ss 57 a7 87 dqs4 118 v ss 28 dq18 58 v dd 88 v ss 119 sa0 29 dq19 59 a5 89 dq34 120 scl 30 v ss 60 a4 90 dq35 121 sa2 91 v ss 122 v tt (sig): signal in brackets may be routed to the socket connector, but is not used on the module
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 backside pin symbol pin symbol pin symbol pin symbol 123 v tt 153 dq29 183 a3 214 dq45 124 v ss 154 v ss 184 a1 215 v ss 125 dq4 155 dm3 185 v dd 216 dm5 126 dq5 156 nc 186 ck0 217 nc 127 v ss 157 v ss 187 ck0# 218 v ss 128 dm0 158 dq30 188 v dd 219 dq46 129 nc 159 dq31 189 v dd 220 dq47 130 v ss 160 v ss 190 e vent # 221 v ss 131 dq6 161 cb4 191 a0 222 dq52 132 dq7 162 cb5 192 v dd 223 dq53 133 v ss 163 v ss 193 ba1 224 v ss 134 dq12 164 dm8 194 v dd 225 d m6 135 dq13 165 nc 195 ras# 226 nc 136 v ss 166 v ss 196 cs0# 227 v ss 137 dm1 167 cb6 197 v dd 228 dq54 138 nc 168 cb7 198 odt0 229 dq55 139 v ss 169 v ss 199 a13 230 v ss 140 dq14 170 nc 200 v dd 231 dq60 141 dq15 171 nc 201 nc 232 dq61 142 v ss 172 nc 20 2 nc 233 v ss 143 dq20 173 v dd 203 v ss 234 dm7 144 dq21 174 (a15)/ nc 204 dq36 235 nc 145 v ss 175 a14 205 dq37 236 v ss 146 dm2 176 v dd 206 v ss 237 dq62 147 nc 177 a12 207 dm4 238 dq63 148 v ss 178 a9 208 nc 239 v ss 149 dq22 179 v dd 209 v ss 240 v ddspd 150 dq23 180 a8 210 dq38 241 sa1 151 v ss 181 a6 211 dq39 242 sda 152 dq28 182 v dd 212 v ss 243 v ss 213 dq44 244 v tt (sig): signal in brackets may be routed to the socket connector, but is not used on the module
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 functional block diagr amm 4096 mb ddr3 sdram mini - dimm, 2 rank and 18 components dq 0 dq 1 dq 2 dq 3 dq 5 dq 4 dq 6 dq 7 s 0 dqs 0 dqs 0 dm 0 dqs 1 dqs 1 dm 1 dq 8 dq 9 dq 10 dq 11 dq 13 dq 12 dq 14 dq 15 dqs 2 dqs 2 dm 2 dq 16 dq 17 dq 18 dq 19 dq 21 dq 20 dq 22 dq 23 dqs 3 dqs 3 dm 3 dq 24 dq 25 dq 26 dq 27 dq 29 dq 28 dq 30 dq 31 dq 32 dq 33 dq 34 dq 35 dq 37 dq 36 dq 38 dq 39 dqs 4 dqs 4 dm 4 dqs 5 dqs 5 dm 5 dq 40 dq 41 dq 42 dq 43 dq 45 dq 44 dq 46 dq 47 dqs 6 dqs 6 dm 6 dq 48 dq 49 dq 50 dq 51 dq 53 dq 52 dq 54 dq 55 dqs 7 dqs 7 dm 7 dq 56 dq 57 dq 58 dq 59 dq 61 dq 60 dq 62 dq 63 v ddspd spd v dd / v ddq d 0 - d 17 v refdq v refca d 0 - d 17 d 0 - d 17 d 0 - d 17 v ss ck 0 , ck 1 notes : 1 . dq - to - i / o wiring is shown as recommended but may be changed . 2 . dq / dqs / dqs / odt / dm / cke / s relationship must be maintained as shown . 3 . dq , dm , dqs / dqs resistors : refer to associated topology diagram . 4 . refer to the appropriate clock wiring topology under the dimm wiring details section of the jeded document . 5 . for each dram , a unique zq resistor is connected to gnd . the zq resistor is 240 o 1 %. 6 . refer to associated figure for spd details . i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 0 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 9 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 1 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 10 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 2 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 11 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 3 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 12 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 4 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 13 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 5 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 14 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 6 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 15 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 7 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 16 dqs cs s 1 cb 0 cb 1 cb 2 cb 3 cb 5 cb 4 cb 6 cb 7 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 8 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 17 dqs cs ba 0 - ba 2 ba 0 - ba 2 : sdram d 0 - d 17 a 0 - a 14 a 0 - a 14 : sdram d 0 - d 17 ras ras : sdram d 0 - d 17 cas cas : sdram d 0 - d 17 we we : sdram d 0 - d 17 odt 0 odt : sdram d 0 - d 8 cke 1 cke : sdram d 9 - d 17 ck : sdram d 0 - d 17 ck 0 , ck 1 ck : sdram d 0 - d 17 reset reset : sdram d 0 - d 17 cke 0 cke : sdram d 0 - d 8 odt 1 odt : sdram d 9 - d 17 dqs 8 dm 8 dqs 8
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 maximum electrical dc characteristics parameter/ condition symbol min max units supply voltage v dd - 0.4 1.975 v i/o supply voltage v dd q - 0.4 1.975 v v dd l supply voltage v dd l - 0.4 1.975 v vol tage on any pin relative to v ss v in , v out - 0.4 1.975 v input leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) i i a command/address ras#, cas#, we#, s#, cke - 16 16 ck, ck# - 16 16 dm - 2 2 output leakage current (dqs and odt are disabled; 0v v out v dd q ) i oz - 5 5 a dq, dqs, dqs# v ref leakage current ; v ref is on a valid level i vref - 8 8 a dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1.425 1.5 1.575 v i/o supply voltage v dd q 1.425 1.5 1.575 v v dd l suppl y voltage v dd l 1.425 1.5 1.575 v i/o reference voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt 0.49 x v dd q - 20mv 0.50 x v dd q 0.51x v dd q +20mv v input high (logic 1) voltage v ih (dc) v ref + 0.1 v dd q + 0.3 v input low (logic 0) voltage v il (dc) - 0.3 v ref C ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac) v ref + 0.175 - v input low (logic 0) voltage v il (ac) - v ref - 0.175 v capacitance at ddr3 data rates, it is recommended to simulate the performance of the module to achieve optimum values. when inductance and delay parameters associated with trace lengths are used in simulations, they are significantly more accurate and realistic than a gr oss estimation of module capacitance. simulations can then render a considerably more accurate result. jedec modules are now designed by using simulations to close timing budgets.
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 i dd specifications and conditions (0c t case + 85c; v dd q = +1.5v 0. 075v, v dd = +1.5v 0.075v) parameter & test condition symbol max. unit 10600 - 999 8500 - 777 operating current *) : one device bank active - precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high between valid commands; dq inputs changin g once per clock cycle; address and control inputs changing once every two clock cycles i dd0 648 603 ma operating current *) : one device bank; active - read - precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 783 738 ma precharge power - down current: all device banks idle; power - down mode; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref fast exit i dd2p 360 360 ma slow exit 216 216 precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all control and address bus inputs are not changing; dqs are floating at v ref i dd2q 540 540 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and address bus inputs are changing once eve ry two clock cycles; dq inputs changing once per clock cycle i dd2n 630 540 ma active power - down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref (always fast exit ) i dd3p 540 540 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycle s; dq inputs changing once per clock cycle i dd3n 990 900 ma operating read current: all device banks open, continuous burst reads; one module rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 1143 1008 ma
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 parameter & test condition symbol max. unit 10600 - 999 8500 - 777 operat ing write current: all device banks open, continuous burst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are ch anging once every two clock cycles; dq inputs changing once per clock cycle i dd4w 1368 1143 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# is high between valid commands; all other control and add ress bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd5 3060 3060 ma self refresh current: ck and ck# at 0v; cke 0.2v; all other control and address bus inputs are floating at v ref ; dqs are floating at v ref i dd6 216 216 ma operating current*) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i d d ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 1998 1638 ma *) value calculated as one module r ank in this operating condition, and all other module ranks in idd2p (cke low) mode. timing values used for i dd measurement i dd measurement conditions symbol 10600 - 999 8500 - 777 unit cl (i dd ) 9 7 t ck t rcd (i dd ) 13.5 13.125 ns t rc (i dd ) 49.5 50.625 ns t rrd (i dd ) 6 7.5 ns t ck (i dd ) 1.5 1. 87 ns t ras min (i dd ) 36 37.5 ns t ras max (i dd ) 70 200 70 200 ns t rp (i dd ) 13.5 13.125 ns t rfc (i dd ) 160 160 ns
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 ddr3 sdram component electrical characteristics and recommended ac operating conditions (0c t cas e + 85c; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 10600 - 999 8500 - 777 parameter symbol min max min max unit clock cycle time cl = 10 t ck (10) 1.5 <1.875 - - ns cl = 9 t ck (9) 1.5 <1.875 - - ns cl = 8 t ck (8) 1.875 <2. 5 - - ns cl = 7 t ck (7) 1.875 <2.5 1.875 <2.5 ns cl = 6 t ck (6) 2.5 3.3 2.5 3.3 ns cl = 5 t ck (5) 3.0 3.3 3.0 3.3 ns ck high - level width t ch (avg) 0.47 0.53 0.47 0.53 t ck ck low - level width t cl (avg) 0.47 0.53 0.47 0.53 t ck data - out high - impedance window from ck/ck# t hz 250 300 ps data - out low - impedance window from ck/ck# t lz - 500 250 - 600 300 ps dq and dm input setup time relative to dqs t ds(base) 30 25 ps dq and dm input hold time relative to dqs t dh(base) 65 100 ps dq and dm input setu p time relative to dqs v ref =1v/ns t ds1v 180 200 ps dq and dm input hold time relative to dqs v ref =1v/ns t dh1v 165 200 ps dq and dm input pulse width ( for each input ) t dipw 400 490 ps dqs, dqs# to dq skew, per access t dqsq 125 150 ps dq - dqs ho ld, dqs to first dq to go non - valid, per access t qh 0.38 0.38 t ck (avg) dqs input high pulse width t dqsh 0.45 0.55 0.45 0.55 t ck dqs input low pulse width t dqsl 0.45 0.55 0.45 0.55 t ck dqs, dqs# rising to/from ck, ck# t dqsck - 255 255 - 300 300 ps dqs , dqs# rising to/from ck, ck# when dll disabled t dqsck dll_dis 1 10 1 10 ns dqs falling edge to ck rising - setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 t ck dqs read preamble t rpre 0.9 note1 0.9 note1 t ck dq s read postamble t rpst 0.3 note2 0.3 note2 t ck dqs write preamble t wpre 0.9 0.9 t ck dqs write postamble t wpst 0.3 0.3 t ck positive dqs latching edge to associated clock edge t dqss - 0.25 + 0.25 - 0.25 + 0.25 t ck address and control input pulse widt h ( for each input ) t ipw 620 780 ps ctrl, cmd, addr setup to ck, ck# t is(base) 65 125 ps ctrl, cmd, addr setup to ck, ck# v ref @ 1v/ns t is(1v) 240 300 ps 1 the maximum preamble is bound by t lzdqs (max) 2 the maximum postamble is bound by t hzdqs (max )
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 ddr3 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 10600 - 999 8500 - 777 parameter symbol min max min max unit ctrl, cmd, addr hold to ck, ck# t ih(base) 140 200 ps ctrl, cmd, addr hold to ck, ck# v ref @ 1v/ns t ih( 1v) 240 300 ps cas# to cas# command delay t ccd 4 4 t ck active to active (same bank) command period t rc 49.5 50.625 ns active bank a to active bank b command t rrd max 4nck,10ns max 4nck,7.5ns ns active to read or write delay t rcd 13.5 13.125 n s four bank activate period 1k page size t faw 30 37.5 ns 2k page size 45 50 active to precharge command t ras 36 70 70 t rtp max 4nck,7.5ns max 4nck,7.5ns ns write recovery time t wr 15 15 ns auto precharge write recovery + precharge time t dal t wr + t rp /t ck t wr + t rp /t ck ns internal write to read command delay t wtr max 4nck,7.5ns max 4nck,7.5ns ns precharge command period t rp 15 13.125 ns load mode command cycle time t mrd 4 4 t ck refresh to active or refresh to refresh command interval t rfc 160 70 0 c t case 85 c t refi 7.8 7.8 s 85 c < t case 95 c t refi it 3.9 3.9 rtt turn - on from odtl on reference t aon - 250 250 - 300 300 ps rtt turn - on from odtl off reference t aof 0.3 0.7 0.3 0.7 t ck asynchronous rtt turn - on delay (power down with dll off ) t aonpd 2 8,5 2 8,5 ns asynchronous rtt turn - off delay (power down with dll off) t aofpd 2 8,5 2 8,5 ns rtt dynamic change skew t adc 0.3 0.7 0.3 0.7 t ck exit self refresh to commands not requiring a locked dll t xs max 5nck,tr fc + 10ns max 5nck,tr fc + 10ns ns write levelling setup from rising ck, ck# crossing to rising dqs, dqs# crossing t wls 195 245 ps write levelling setup from rising dqs, dqs# crossing to rising ck, ck# crossing t wlh 195 245 ps first dqs, dqs# rising edge t wlmrd 40 40 t ck dqs, dqs# delay t wldqsen 25 25 t ck
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 ddr3 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q = +1.5v 0.075v, v dd = +1.5v 0.075v) ac characteristics 10600 - 999 8500 - 777 para meter symbol min max min max unit exit reset from cke high to a valid command t xpr max 5nck, t rfc + 10ns max 5nck, t rfc + 10ns begin power supply ramp to power supplies stable t v ddpr 200 200 ms reset# low to power supplies stable t rps 200 200 m s reset# low to i/o and rtt high - z t ioz 20 20 ns exit precharge power - down to any non - read command t xp max 3nck,6ns max 3nck,7.5ns cke minimum high/low time t cke max 3nck, 5.625ns max 3nck, 5.625ns temperature sensor with serial presence - det ect eeprom temperature sensor with serial presence - detect eeprom operating conditions parameter / condition symbol min max unit supply voltage v ddspd +3 +3.6 v supply current: v dd = 3.3v i dd +2.0 ma input high voltage: l ogic 1; scl, sda v ih +1.45 v ddspd +1 v input low voltage: logic 0; scl, sda v il - 550 mv output low voltage: i out = 2.1ma v ol - 400 mv input current i in - 5.0 5.0 a temperature sensing range tbd tbd c temperature sensor accuracy tbd tbd c s c l s d a e v e n t s a 2 s a 1 s a 1 s a 0 s a 0 e v e n t w p / r 1 0
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 a.c. characteristics of temperature sensor v cc = 3.3 v 10%, t a = ?40c to +125c symbol parameter / condition min max unit f scl scl clock frequency 10 400 khz t buf bus free time between stop and start 1300 ns t f sda fall time 300 ns t r sda rise time 3 00 ns t hd:dat data hold time (accepted for input data) 0 ns data hold time (guaranteed for output data) 300 900 ns t h:sta start condition hold time 600 ns t high high period of scl 600 ns t low low period of scl 1300 ns t su:dat data setup time 100 ns t su:sta start condition setup time 600 ns t su:sto stop condition setup time 600 ns t timeout smbus scl clock low timeout 25 35 ms t i noise pulse filtered at scl and sda inputs 100 ns t wr write cycle time 5 ms t pu power - up delay to valid tempe rature recording 100 ms temperature characteristics of temperature sensor v cc = 3.3 v 10%, t a = ?40c to +125c parameter test conditions/comments max unit temperature reading error class b, jc42.4 compliant +75c t a +95c, active range +40c t a +125c, monitor range 40c t a +125c, sensing range 1 ja junction - to - ambient (still air) 92 c/w 1 power dissipa tion is defined as p j = (t j ? t a )/ ja , where tj is the junction temperature and ta is the ambient temperature. the thermal resistance value refers to the case of a package being used on a standard 2 - layer pcb. slave address bits of temperature sensor devi ce device type identifier select address signals r/w# b7 1 b6 b5 b4 b3 b2 b1 b0 eeprom 1 0 1 0 a 2 a 1 a 0 r/w# temp. sensor 0 0 1 1 a 2 a 1 a 0 r/w# 1 the most significant bit, b7, is sent first.
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 14 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 heatspreader: two part anodized aluminium 1050, attached wi th adhesive thermally conductive tape adhesive thermal ly conductive tape: ppi - tc - 150b or equivalent : property ppi - tc 150b test methodology carrier type filled acry l at e adhesive thickness 0.15 mm bs 3924 total thickness 0.15 mm +/ - 10% color white holding power (kg/cm) > 0.08 (kg/cm) bs 3924 180 peel off force (kg/25mm) 30min r.t. > 1.2 bs 3924 thermal conductivity (w/m k) 0.5 din v 54462 insulation strength (kv) 3.5 astm d - 149 ppi - tc 150b ppi - tc 250b ppi - tc 500b ppi - tc 1000b testmethode conformal coating: ? dip coated with humiseal 1a33 ? coating thickness 1 - 3 mils ? coating covers complete module surface except gold edge connector. 2 4 . 5 m m + / - 0 . 1 m m 7 4 . 0 m m + / - 0 . 2 m m 2 5 . 5 m m + / - 0 . 1 m m 7 4 . 0 m m + / - 0 . 2 m m t o p p a r t b o t t o m p a r t 2 . 9 m m + / - 0 . 1 m m 2 . 9 m m + / - 0 . 1 m m t h i c k n e s s : 0 . 5 m m + / - 0 . 0 5 m m a l u m i n u m 1 1 0 0 c o l o r : a n o d i z e d c y a n b l u e
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 15 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 serial presence - detect matrix byte byte description 10600 - 999 0 crc range, e eprom bytes, bytes used 0x92 1 spd revison 0x1 1 2 dram device type 0x0b 3 module type (form factor) 0x0 6 4 sdram device density & banks 0x0 3 5 sdram device row & column count 0x1 9 6 byte 6 reserved 0x00 7 module ranks & device dq count 0 x0 9 8 ecc t ag & module memory bus width 0x0 b 9 fine timebase dividend/divisor 0x 11 10 medium timebase dividend 0x01 11 medium timebase divisor 0x08 12 min sdram cycle time ( t ck min ) 0x0c 13 byte 13 reserved 0x00 14 cas latencies supported (cl4 => cl11) 0x3 e 15 cas latencies supported (cl12 => cl18) 0x00 16 min cas latency time ( t aa min ) 0x69 17 min write recovery time ( t wr min ) 0x78 18 min ras# to cas# delay ( t rcd min ) 0x69 19 min row active to row active delay ( t rrd min ) 0x30 20 min row precharge delay ( t rp min ) 0x69 21 upper nibble for t ras & t rc 0x11 22 min active to precharge delay ( t ras min ) 0x20 23 min active to active/refresh delay ( t rc min ) 0x89 24 min refresh recovery delay ( t rfc min ) lsb 0x0 0 25 min refresh recovery delay ( t rfc min ) msb 0x0 5 26 min internal write to read cmd delay ( t wtr min ) 0x3c 27 min internal read to precharge cmd delay ( t rtp min ) 0x3c 28 min four active window delay ( t faw min ) msb 0x00 29 min four active window delay ( t faw min ) lsb 0xf0 30 sdram device output drivers supported 0x8 3 31 sdram device thermal & refresh options 0x 0 1
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 16 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 byte byte description 10600 - 999 32 ddr3 - module thermal sensor 0x 8 0 33 ddr3 - sdram device type 0x00 34 ddr3 - fine offset for t ckmin 0x00 3 5 - 59 bytes 33 - 59 reserved 0x00 60 module height ( nominal) 0x0f 61 module thickness (max) 0x 22 62 reference raw card id 0x 01 63 address mapping edge conector to dram 0x00 64 ddr3 - heatspreader solution 0x80 6 5 - 116 bytes 64 - 116 reseved 0x00 117 module mfr id (lsb) 0x83 118 module mfr id (msb) 0 x da 1 19 module mfr location id 0x01 (swi t zerland) 0x02 (germany) 0x03 (usa) 120 module mfr year x 121 module mfr week x 122 - 125 module serial number x 126 - 127 crc 0x 6225 128 - 145 module part number " sg l 04g72 b 1b d 2sa - xx" 146 module die rev x 147 module pcb rev x 148 dram device mfr id (lsb) 0x80 149 dram device mfr (msb) 0xc e 150 - 175 mfr reserved bytes 150 - 175 0x00 176 - 255 customer reserved bytes 176 - 255 0x ff
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 17 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 part number code s g l 04g 72 b 1 b d 2 sa - cc * r t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 *rohs compl. swissbit ag ddr3 - 1333 mt/s 1.5v d dr 3 2 4 4 pin mini - udi mm chip vendor ( samsung ) depth ( 4 gb) 2 module rank s width chip rev. d pcb - type ( ba3s782 1.00 ) chip organisation x8 * optional / additional information t= thermal sensor
preliminary data sheet rev.0.9 04.08.2011 swissbit ag industriestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 18 ch C 9552 br onschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 18 locations swissbit ag industriestrasse 4 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 _____________________________ swissbit na, inc. 18 willett avenue, suite 202 port chester, ny 10573 usa phone: +1 914 935 1400 fax: +1 914 935 9865 _____________________________ swissbit na, inc. 1202 e. winding creek drive eagle, id 83616 usa phone: +1 208 870 4525 fax: +1 208 870 4525 _____________________________ swissbit japan, inc. 3f core koenji, 2 - 1 - 24 koenji - kita, sugi nami - ku, tokyo 166 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512

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